Several engineering applications are employed to demonstrate the performance of parallel FDTD method enhanced by SSE instruction set. The benchmarks of the SSE acceleration on both the multi-CPU workstation and computer cluster have demonstrated the advantages of (vector arithmetic logic unit) VALU acceleration over GPU acceleration. The implementation of SSE instruction set to parallel FDTD method has achieved the significant improvement on the simulation performance.
We introduce a hardware acceleration technique for the parallel finite difference time domain (FDTD) method using the SSE (streaming (single instruction multiple data) SIMD extensions) instruction set.
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